/* This file is part of the libopencm3 project.
 *
 * It was generated by the irq2nvic_h script.
 *
 * These definitions bend every interrupt handler that is defined CMSIS style
 * to the weak symbol exported by libopencm3.
 */

#define CPU2CPU_INT0_IRQHandler cpu2cpu_int0_isr
#define CPU2CPU_INT1_IRQHandler cpu2cpu_int1_isr
#define CPU2CPU_INT2_IRQHandler cpu2cpu_int2_isr
#define CPU2CPU_INT3_IRQHandler cpu2cpu_int3_isr
#define DIRECTED0_SEMA4_IRQHandler directed0_sema4_isr
#define DIRECTED1_MCM_IRQHandler directed1_mcm_isr
#define DIRECTED2_IRQHandler directed2_isr
#define DIRECTED3_IRQHandler directed3_isr
#define DMA0_IRQHandler dma0_isr
#define DMA0_ERROR_IRQHandler dma0_error_isr
#define DMA1_IRQHandler dma1_isr
#define DMA1_ERROR_IRQHandler dma1_error_isr
#define RESERVED0_IRQHandler reserved0_isr
#define RESERVED1_IRQHandler reserved1_isr
#define MSCM_ECC0_IRQHandler mscm_ecc0_isr
#define MSCM_ECC1_IRQHandler mscm_ecc1_isr
#define CSU_ALARM_IRQHandler csu_alarm_isr
#define RESERVED2_IRQHandler reserved2_isr
#define MSCM_ACTZS_IRQHandler mscm_actzs_isr
#define RESERVED3_IRQHandler reserved3_isr
#define WDOG_A5_IRQHandler wdog_a5_isr
#define WDOG_M4_IRQHandler wdog_m4_isr
#define WDOG_SNVS_IRQHandler wdog_snvs_isr
#define CP1_BOOT_FAIL_IRQHandler cp1_boot_fail_isr
#define QSPI0_IRQHandler qspi0_isr
#define QSPI1_IRQHandler qspi1_isr
#define DDRMC_IRQHandler ddrmc_isr
#define SDHC0_IRQHandler sdhc0_isr
#define SDHC1_IRQHandler sdhc1_isr
#define RESERVED4_IRQHandler reserved4_isr
#define DCU0_IRQHandler dcu0_isr
#define DCU1_IRQHandler dcu1_isr
#define VIU_IRQHandler viu_isr
#define RESERVED5_IRQHandler reserved5_isr
#define RESERVED6_IRQHandler reserved6_isr
#define RLE_IRQHandler rle_isr
#define SEG_LCD_IRQHandler seg_lcd_isr
#define RESERVED7_IRQHandler reserved7_isr
#define RESERVED8_IRQHandler reserved8_isr
#define PIT_IRQHandler pit_isr
#define LPTIMER0_IRQHandler lptimer0_isr
#define RESERVED9_IRQHandler reserved9_isr
#define FLEXTIMER0_IRQHandler flextimer0_isr
#define FLEXTIMER1_IRQHandler flextimer1_isr
#define FLEXTIMER2_IRQHandler flextimer2_isr
#define FLEXTIMER3_IRQHandler flextimer3_isr
#define RESERVED10_IRQHandler reserved10_isr
#define RESERVED11_IRQHandler reserved11_isr
#define RESERVED12_IRQHandler reserved12_isr
#define RESERVED13_IRQHandler reserved13_isr
#define USBPHY0_IRQHandler usbphy0_isr
#define USBPHY1_IRQHandler usbphy1_isr
#define RESERVED14_IRQHandler reserved14_isr
#define ADC0_IRQHandler adc0_isr
#define ADC1_IRQHandler adc1_isr
#define DAC0_IRQHandler dac0_isr
#define DAC1_IRQHandler dac1_isr
#define RESERVED15_IRQHandler reserved15_isr
#define FLEXCAN0_IRQHandler flexcan0_isr
#define FLEXCAN1_IRQHandler flexcan1_isr
#define RESERVED16_IRQHandler reserved16_isr
#define UART0_IRQHandler uart0_isr
#define UART1_IRQHandler uart1_isr
#define UART2_IRQHandler uart2_isr
#define UART3_IRQHandler uart3_isr
#define UART4_IRQHandler uart4_isr
#define UART5_IRQHandler uart5_isr
#define SPI0_IRQHandler spi0_isr
#define SPI1_IRQHandler spi1_isr
#define SPI2_IRQHandler spi2_isr
#define SPI3_IRQHandler spi3_isr
#define I2C0_IRQHandler i2c0_isr
#define I2C1_IRQHandler i2c1_isr
#define I2C2_IRQHandler i2c2_isr
#define I2C3_IRQHandler i2c3_isr
#define USBC0_IRQHandler usbc0_isr
#define USBC1_IRQHandler usbc1_isr
#define RESERVED17_IRQHandler reserved17_isr
#define ENET0_IRQHandler enet0_isr
#define ENET1_IRQHandler enet1_isr
#define ENET0_1588_IRQHandler enet0_1588_isr
#define ENET1_1588_IRQHandler enet1_1588_isr
#define ENET_SWITCH_IRQHandler enet_switch_isr
#define NFC_IRQHandler nfc_isr
#define SAI0_IRQHandler sai0_isr
#define SAI1_IRQHandler sai1_isr
#define SAI2_IRQHandler sai2_isr
#define SAI3_IRQHandler sai3_isr
#define ESAI_BIFIFO_IRQHandler esai_bififo_isr
#define SPDIF_IRQHandler spdif_isr
#define ASRC_IRQHandler asrc_isr
#define VREG_IRQHandler vreg_isr
#define WKPU0_IRQHandler wkpu0_isr
#define RESERVED18_IRQHandler reserved18_isr
#define CCM_FXOSC_IRQHandler ccm_fxosc_isr
#define CCM_IRQHandler ccm_isr
#define SRC_IRQHandler src_isr
#define PDB_IRQHandler pdb_isr
#define EWM_IRQHandler ewm_isr
#define RESERVED19_IRQHandler reserved19_isr
#define RESERVED20_IRQHandler reserved20_isr
#define RESERVED21_IRQHandler reserved21_isr
#define RESERVED22_IRQHandler reserved22_isr
#define RESERVED23_IRQHandler reserved23_isr
#define RESERVED24_IRQHandler reserved24_isr
#define RESERVED25_IRQHandler reserved25_isr
#define RESERVED26_IRQHandler reserved26_isr
#define GPIO0_IRQHandler gpio0_isr
#define GPIO1_IRQHandler gpio1_isr
#define GPIO2_IRQHandler gpio2_isr
#define GPIO3_IRQHandler gpio3_isr
#define GPIO4_IRQHandler gpio4_isr
